sdc-14610/15 series three channel 14- and 16-bit tracking s/d converters description the sdc-14610/15 series are small low cost triple synchro- or resolver-to-digital converters. the sdc-14610 series is fixed at 14 bits, the sdc-14615 at 16 bits. the three channels are indepen- dent tracking types but share digital out- put pins and a common reference. the velocity output (vel) from the sdc-14610/15 series, which can be used to replace a tachometer, is a 4 v signal referenced to ground with a lin- earity of 1% of output voltage. a bit output is optional and is a logic line that indicates los (loss of signal) or excessive converter error. due to pin limitations this option will exclude the velocity output. sdc-14610/15 series convert- ers are available with operating temperature ranges of 0c to +70c and -55c to +125c, and mil-prf-38534 processing is available. applications with its low cost, small size, high accuracy, and versatile perfor- mance, the sdc-14610/15 series converters are ideal for use in mod- ern high-performance military and industrial position control systems. typical applications include radar antenna positioning, navigation and fire control systems, motor control, and robotics. features ? fixed 14- or 16-bit resolution ? small size 36-pin ddip package ? three independent converters ? low cost ? velocity output eliminates tachometer ? optional bit output ? high reliability single chip monolithic ? -55c to +125c operating temperature range ? mil-prf-38534 processing available s1 s2 s3 input option control transformer gain demodulator r i c i vel integrator hysteresis vco & timing 14/16-bit up/down counter data latch em data el 8 inh (common) s4 +ref -ref bit detector reference conditioner error bit r los optional ? 1991 ilc data device corporation figure 1. sdc-14610/15 block diagram (one channel)
2 table 1. sdc-14610/15 specifications (each channel) these specs apply over the rated power supply, temperature, and refer- ence frequency ranges; 10% signal amplitude variation, and 10% har- monic distortion. values are for each channel unless stated otherwise. parameter unit value resolution bits 14 16 accuracy min 4 + 1 lsb 2(4) + 1 lsb repeatability lsb 1 max reference input type differential linearity lsb (+ref, -ref ), common to all channels differential 1 max voltage range frequency input impedance single ended differential common mode range vrms hz ohm ohm vpeak 2 & 11.8 v units 2-35 360-5000 60k 120k 50, 100 transient 90 v unit 10-130 see note 270k min 540k min 200 300 transient signal input characteristics 90 v synchro input (l-l) zin line-to-line zin line-to-ground common mode voltage 11.8 v synchro input (l-l) zin line-to-line zin line-to-ground common mode voltage 11.8 v resolver input (l-l) zin line-to-line zin line-to-ground common mode voltage 2 v direct input (l-l) voltage range max voltage no damage input impedance ohm ohm v ohm ohm v ohm ohm v vrms v ohm each channel 123k 80k 180 max 52k 34k 30 max 140k 70k 30 max 2 nom, 2.3 max 25 cont, 100 pk transient 20 m//10 pf min digital input/output logic type inputs inhibit (lnh)(common) enable bits 1 to 8 (em) enable bits 9 to 14(16) (el) outputs parallel data [1-14(16)] bits note: 47 - 5k for 90 v, 60 hz; 360 - 5k for 90 v, 400 hz table 1. sdc 14610/15 specifications (continued) parameter unit value digital input/output outputs (continued) built-in-test (bit)(optional) drive capability ttl cmos dynamic characteristics each channel input frequency bandwidth(closed loop) ka a1 a2 a b resolution tracking rate typical minimum acceleration (1 lsb lag) settling time (179 step max) hz hz 1/s 2 1/s 1/s 1/s 1/s bits rps rps deg/s 2 msec device type 60 hz 400 hz 47-5 k 15 830 0.17 5k 29 14.5 14 1.25 1 18 1100 16 0.31 0.25 4.5 2500 360-5 k 103 53k 1.33 40k 230 115 14 10 8 1160 140 16 2.5 2 290 320 velocity characteristics polarity voltage range(full scale) voltage scaling scale factor scale factor tc reversal error linearity zero offset zero offset tc load noise v rps/fs % ppm/c % % mv v/c kohm (vp/v)% each channel positive for increasing angle 4.5 typ,4 min 10 10 typ 20 max 100 typ 200 max 1 typ 2 max 0.5 typ 1 max 5 typ 10 max 15 typ 30 max 20 max 1 typ 2 max power supplies nominal voltage voltage range max volt. w/o damage current (ea.) v % v ma total device +5 -5 510 +7 -7 36 typ, 51 max temperature range operating -30x -10x storage c c c 0 to +70 -55 to +125 -65 to +150 physical characteristics size weight 1.70 x 0.78 x 0.21 (43.2 x 19.8 x 5.3) 0.66 in (mm) oz logic 0 = bit condition 100 lsbs of error with a fil- ter of 500 s or los. each channel 50 pf + logic 0; 1 ttl load, 1.6 ma at 0.4 v max logic 1; 10 ttl loads, -0.4 ma at 2.8 v min logic 0; 100 mv max driving logic 1; +5 v supply minus 100 mv min driving ttl/cmos compatible logic 0 = 0.8 v max. logic 1 = 2.0 v min. loading (per channel) =10 a max p.u. current source to +5 v //5 pf max. cmos transient protected each channel logic 0 inhibits; data stable within 0.5 s logic 0 enables; data stable within 150 ns logic 1 = high impedance data high z within 100 ns common to all channels 8 parallel lines; 2 bytes natural binary angle, positive logic
theory of operation the sdc-14610/15 series of converters are based upon a sin- gle chip cmos custom monolithic. they are implemented using the latest ic technology which merges precision analog circuitry with digital logic to form a complete high performance tracking resolver-to-digital converter. figure 1 is the functional block diagram of sdc-14610/15 series. the converter operates with 5 vdc power supplies. analog signals are referenced to analog ground, which is at ground potential. the converter is made up of three main sec- tions; an input front-end, a converter, and a digital interface. the converter front-end differs for synchro, resolver and direct inputs. an electronic scott-t is used for synchro inputs, a resolver con- ditioner for resolver inputs and a sine and cosine voltage follow- er for direct inputs. these amplifiers feed the high accuracy control transformer (ct). its other input is the 14-bit digital angle f . its output is an analog error angle, or difference angle, between the two inputs. the ct performs the ratiometric trigono- metric computation of sin q cos f - cos q sin f = sin( q - f ) using amplifiers, switches, logic and capacitors in precision ratios. the converter accuracy is limited by the precision of the com- puting elements in the ct. in these converters, ratioed capacitors are used in the ct instead of more conventional precision ratioed resistors. capacitors used as computing elements with op-amps need to be sampled to eliminate voltage drifting. therefore, the circuits are sampled at a high rate to eliminate this drifting and at the same time to cancel out the op-amp offsets. the error processing is performed using the industry standard technique for type ii tracking r/d converters. the dc error is integrated yielding a velocity voltage which, in turn, drives a volt- age controlled oscillator (vco). this vco is an incremental inte- grator (constant voltage input to position rate output) which, together with the velocity integrator, forms a type ii servo feed- back loop. a lead in the frequency response is introduced to sta- bilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. transfer function and bode plot the dynamic performance of the converter can be determined from its functional block diagram and its bode plots (open and closed loop); these are shown in figures 1 and 2 respectively. the open loop transfer function is as follows: s a 2 +1 b ( ) open loop transfer function = s s 2 +1 10b ( ) where a is the gain coefficient and b is the frequency of lead compensation the components of gain coefficient are error gradient, integrator gain, and vco gain. these can be broken down as follows: - error gradient = 0.011 volts per lsb (ct+error amp+demod) 1 - integrator gain = volts per second per volt r i c i 1 - vco gain = lsbs per second per volt 1.25 r v c v general setup considerations the following recommendations should be considered when connecting the sdc-14610/15 series converters: 1) power supplies are 5 vdc. for lowest noise performance it is recommended that a 0.1 f or larger cap be connected from each supply to ground near the converter package. 2) direct inputs are referenced to agnd. 3) connect pin 5 (gnd) to pin 6 (agnd) close to the hybrid. inhibit and enable timing the inhibit (inh) signal is used to freeze the digital output angle in the transparent output data latch while data is being trans- ferred. application of an inhibit signal does not interfere with the continuous tracking of the converter. as shown in figure 3, angular output data is valid 500 nanoseconds maximum after the application of the low-going inhibit pulse. output angle data is enabled onto the tri-state data bus in six bytes. the enable msb (em-a, em-b, or em-c) is used for the most significant 8 bits and enable lsb (el-a, el-b, or el-c) is used for the least significant bits. as shown in figure 4, output data is valid 150 nanoseconds maximum after the application of a low-going enable pulse. the tri-state data bus returns to the high impedance state 100 nanoseconds maximum after the ris- ing edge of the enable signal. 3 -12 db/oct gain = 4 ba 2a -6 db/oct 10b w (rad/sec) 2a 2 2 a w (rad/sec) f = bw = 3db 2 a (hz) p closed loop open loop - gain = 0.4 (b=a/2) (critically damped) figure 2. bode plots
4 bit, built-in-test (optional) this output is a logic line that will flag an internal fault condition, or los (loss-of-signal). the internal fault detector monitors the internal error and, when it exceeds 100 lsbs, will set the line to a logic 0; this condition will occur during a large-step input and will reset to a logic 1 after the converter settles out. (the error voltage is filtered with a 500 s filter) bit will set for an overve- locity condition because the converter loop cant maintain input/output sync. bit will also be set if a total los (loss of all signals) occurs. no false 180 hangup this feature eliminates the false 180 reading during instanta- neous 180 step changes; this condition most often occurs when the input is electronically switched from a digital-to-synchro converter. if the msb (or 180 bit) is toggled on and off, a con- verter without the false 180 reading feature may fail to respond. the condition is artificial, as a real synchro or resolver cannot change its output 180 instantaneously. the condition is most often noticed during wraparound verification tests, simulations, or troubleshooting. enable 150 ns max data data valid 100 ns max high z high z data data valid 500 ns max inhibit 1.895 0.005 (48.1 0.13) 1.700 0.005 (43.2 0.13) 0.018 (0.46) diam typ 0.100 typ(2.54) tol. non- cumulative 0.21 max (5.3) dot identifies pin 1 0.775 0.005 (19.7 0.13) 0.600 0.005 (15.2 0.13) 0.09 0.01 (2.3 0.25) 0.10 0.01 (2.5 0.3) side view bottom view 0.25 min (6.4) 0.015 max (0.39) seating plane 0.055 (1.4) rad typ 0.086 typ radius table 2. pinouts (36 pin) (see note 1) 1 s1a(s) s1a(r) n.c. 36 2 s2a(s) s2a(r) +cosa(d) 36 em-a (enable msbs) 3 s3a(s) s3a(r) +sina(d) 34 el-a (enable lsbs) 4 n.c. s4a(r) n.c. 33 inh (inhibit) 5 gnd (ground)(see note 4) 32 6 agnd (analog ground) (see note 4) 31 em-b (enable msbs) 7 s1b(s) s1b(r) n.c. 30 el-b (enable lsbs) 8 s2b(s) s2b(r) +cosb(d) 29 bit 8/bit 16 (see note 3) 9 s3b(s) s3b(r) +sinb(d) 28 bit 7/bit 15 (see note 3) 10 n.c. s4b(r) n.c. 27 bit 6/bit 14 11 -5 v (power supply) 26 bit 5/bit 13 12 +5 v (power supply) 25 bit 4/bit 12 13 s1c(s) s1c(r) n.c. 24 bit 3/bit 11 14 s2c(s) s2c(r) +cosc(d) 23 bit 2/bit 10 15 s3c(s) s3c(r) +sinc(d) 22 bit 1/bit 9 16 n.c. s4c(r) n.c. 21 17 -ref (-reference input) 20 el-c (enable lsbs) 18 +ref (+reference input) 19 em-c (enable msbs) figure 3. inhibit timing figure 4. enable timing notes: 1. dimensions are in inches (millimeters). 2. lead identification numbers are for reference only. 3. lead clusters shall be centered within 0.01 of outline dimensions. lead spac- ing dimensions apply only at seating plane. 4. pin material meets solderability requirements to mil-std-202e, method 208c. 5. case is electrically floating. figure 5. sdc-14610/15 mechanical outline notes: 1. (s) = synchro; (r) = resolver; (d) = 2 v resolver direct 2. replaced with bit - t option 3. sdc-14615 series only 4. connect pin 5 (gnd) to pin 6 (agnd) close to the hybrid vel a (velocity output) (see note 2) vel b (velocity output) (see note 2) vel c (velocity output) (see note 2)
5 ordering information sd-1461xt-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above accuracy: 2 = 4 + 1 lsb 4 = 2 minutes + 1 lsb (not available with 14-bit units.) process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data output option: blank = standard velocity output (vel) t = built-in-test output, instead of vel input option: 0 = 11.8 v, synchro, 14 bit, 400 hz 1 = 11.8 v, resolver, 14 bit, 400 hz 2 = 90 v, synchro, 14 bit, 400 hz 3 = 2 v, direct, 14 bit, 400 hz 4 = 90 v, synchro, 14 bit, 60 hz 5 = 11.8 v, synchro, 16 bit, 400 hz 6 = 11.8 v, resolver, 16 bit, 400 hz 7 = 90 v, synchro, 16 bit, 400 hz 8 = 2 v, direct 16 bit, 400 hz 9 = 90 v, synchro, 16 bit, 60 hz *standard ddc processing with burn-in and full temperature testsee table below. standard ddc processing mil-std-883 test method(s) condition(s) inspection 2009, 2010, 2017, and 2032 seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 a burn-in 1015, table 1
6 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. h-09/98-1m printed in the u.s.a. ilc data device corporation registered to iso 9001 file no. a5976 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7389 or 7413 headquarters - tel: (631) 567-5600 ext. 7389 or 7413, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com
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